1. Field
Example embodiments relate to semiconductor devices, for example, to cascode-type current mode comparators which may improve signal-to-noise ratio (SNR), and a semiconductor device having the same.
2. Description of the Conventional Art
A semiconductor device may exchange data with another semiconductor device with a voltage signal and/or a current signal. When transmitting data at high speeds, a current signal may be used instead of a voltage signal. To interpret the current signal, the semiconductor device may require a current mode receiver that receives the current signal and extracts the current signal's data. The current mode receiver may use a current mode comparator that outputs CMOS level voltage signals (e.g., data) based on the difference between the received data current and a chosen reference current.
FIG. 1 is a circuit diagram of a conventional current mode receiver. A conventional current mode receiver 100 may include a signal receiving end 110 and a comparator 120. The information corresponding to input current Idata and reference current Iref is presented as a change in a voltage V1 of a node NO1. The change in the voltage V1 of the node NO1 may be converted to a CMOS level voltage signal RxData by comparator 120 which includes the two NAND gates ND1 and ND2.
The comparator 120 may further include two transistors MN and MP which may be used to limit the level of the voltage V1 of the first node NO1. The two transistors MN and MP may be operated in the saturation region. One of the two transistors may be operated according to the relative amount of the input current Idata and the reference current Iref.
If the input current Idata is less than the reference current Iref, the voltage V1 of the first node NO1 increases. For example, it may increase to a level of VDD/2, such that a voltage V2 of a node NO2 transitions to a low level and the voltage signal RxData transitions to a high level. The NMOS transistor MN may then be turned off and the PMOS transistor MP may then be turned on so that current In (a current as much as Iref minus Idata) may flow to ground via the PMOS transistor MP. The NMOS transistor MN may then be turned off so that the voltage V1 of the node NO1 is stabilized.
If the input current Idata is greater than the reference current Iref, the voltage V1 of the first node NO1 may transition to a low level. The voltage V2 of the node NO2 may then transition to a high level and the voltage signal RxData may transition to a low level. The NMOS transistor MN may be turned on and the PMOS transistor MP may be turned off so that current Ip (a current as much as Idata minus Iref) may be supplied to the first node NO1 via the NMOS transistor MN. The PMOS transistor MP may be turned off so that the voltage V1 of the first node NO1 is stabilized.
Because the DC voltage level of the node NO1 may have a theoretical range of [VSS+Vthp˜VDD−Vthn] (a range reduced to a threshold voltage value of the NMOS transistor MN and the PMOS transistor MP), receipt of high speed signals may be improved compared to an example where the voltage V1 of the node NO1 has a CMOS level. However, the level of the voltage V1 of the node NO1 may actually be determined by the amount of input current and output impedance ROUT as shown in Equation 1.
                              Δ          ⁢                                          ⁢          V                =                                            R              OUT                        ×            Δ            ⁢                                                  ⁢            I                    =                                                                      (                                      R                    ⁢                                                                                  ⁢                    1                    ⁢                                                                                                        ⁢                    R                    ⁢                                                                                  ⁢                    2                                    )                                ·                Δ                            ⁢                                                          ⁢              I                        ≈                                          (                                                      1                                          g                      mn                                                        +                                      1                                          g                      mp                                                                      )                            ⁢                                                                                    I                    DATA                                    -                                      I                    REF                                                                                                                          [                  Equation          ⁢                                          ⁢          1                ]            
In Equation 1, ΔV may be change in the level of the voltage V1 of the first node NO1, R1 may be the output impedance of the receiving end 110, R2 may be the input impedance of the comparator 120, gmn may be the transconductance of the NMOS transistor MN, and gmp may be the transconductance of the PMOS transistor MP.
The output impedance R1 of the receiving end 110 may be over several hundred kΩ, whereas the input impedance R2 of the comparator 120 may be 1/gmn or 1/gmp, which may be a relatively small value of several kΩ. Thus, in a system having a low current level (e.g., several hundred microamperes (μA)), the level of the voltage V1 of the node NO1 may be less than several hundred millivolts (mV). Accordingly, the voltage margin of the NAND gate ND1 of the comparator 120 is reduced such that signal receiving at high speeds may be difficult (e.g., low voltage swing level). Another factor which may restrict the comparator 120 is that the voltage noise of the power VDD and VSS may be applied to the first node NO1 without filtering.
As described above, the conventional current mode comparator 100 may be weak in view of noise immunity due to a low voltage swing level and a low power supply rejection ratio (PSRR).